Typical computer integer or fixed-point multiply instructions are implemented such that an associated computer will take two operands each N-bits wide and multiply them together to produce a result 2N-bits wide. Being 2N bits wide, the result needs to be stored, typically, in two separate registers each N-bits wide. To get both N-bit portions of the result, typically two separate instructions need to be executed by the computer. The first instruction stores the high N-bits of the result in a first register and the second instruction stores the low n-bits of the result in a second register with both the first and second registers being N-bits wide. FIG. 1 illustrates the multiply process where two 2-bit operands 101 and 103 are multiplied together by a multiplier 105 to produce a 4-bit result 107. The result 107 is then stored in two 2-bit registers 109 and 111 where register 109 holds bits R1-R2 and register 111 holds bits R3-R4.
In many applications the entire 2N-bit result is not required but instead a subset of the 2N-bits is of interest. If this is just the low or high N-bits, then one instruction suffices. However, an application may require the middle N-bits of the result of a multiply operation. To position the middle resultant N-bits (a subresult) into a single N-bit register requires multiple multiply and post multiply operations.
The present invention is a computer instruction and apparatus that provides for an improved way to align a subresult of a multiply instruction such that the subresult is stored into a single computer register without requiring post multiply operations.